Memory devices are able to write externally supplied data into internal memory cells, and read out the data stored in the internal memory cells.
Conventionally, as shown in FIG. 1, data are written into a memory 1 in a writing mode and output in accordance with externally output addresses, to be transferred after being amplified by a sense amplifier 2.
The data output through the sense amplifier 2 are supplied through a transistor TR1 to an output buffer 3, and then output through an output path (not shown) to the outside.
Under this condition, in order to improve the reading speed of the data of the memory 1, the data line for reading out the data of the memory 1 has to be precharged prior to reading out the data of the memory 1.
That is, as shown in FIG. 2, an MOS transistor N1 is turned on according to a clock signal CK1 which is supplied wherever the address input through address lines A0-A7 is changed. When the MOS transistor N1 is turned on, a power voltage Vcc which is supplied to the drain of the MOS transistor N1 is output to the source of the MOS transistor N1 and the data line which is connected to the source is precharged with the voltage Vcc.
Under this condition, in the case where the data line is precharged by the MOS transistor N1, if data "1" is to be read after reading data "0", a considerable time is required until the data "1" is read after precharging the data line.
If the size of the precharging MOS transistor N1 is increased in an attempt to overcome the above described problem, then the data line is charged with too high a voltage, thereby making it impossible to read the data "0".
Further, the precharging time of the MOS transistor N1 is always kept constant, and therefore, the precharge state is continued even after the completion of the precharge, thereby making the data processing speed slower.